Zero Delay Simulations

Introduction

A few days ago, I stumbled upon an article that described Synchronous and Asynchronous resets. Going through the post I saw the waveforms with the post as well.

And the corresponding testbench:

All this seems correct, however if you look closely at the waveforms you will notice that the Output(Q) of the D-Flip Flop is updated at the same edge as it saw the Input(D). This is not the expected behavior for an edge triggered device. This post takes this example to illustrate how interpretation of HDL based design/testbenches (specifically when it involves sequential elements) by the simulator can confuse someone of the actual behavior of hardware.

Digging Deeper

To replicate this using a D Flip Flop, I wrote a simple example design for 2 D-FF’s and testbench:

And the testbench:

Since this is a very straight-forward example one would expect the behavior of the Flip-Flop to be such that the Output(Q) toggles at the next clock edge whenever there is a toggle on the D-Input. So the above testbench generates the following waveform:

But as you probably noticed above the Output(Q) is changing at the same edge as the Input(D). A casual review of the design and testbench again might not reveal anything. I simulated these using NCVerilog and the simulator wasn’t at fault either.

The issue and the solution

To understand the reason for the above behavior:

• Zero-delay simulations do not consider delays. They do not consider setup/hold time requirements of a sequential element.
• The synthesised gate level model simulations are usually the accurate representation of sequential elements where such a case would lead to X-Propagation like in real silicon.
• The above behavior is primarily due to ignoring what the regions offer of Verilog while modelling the testbench. (Used all NBA statements inside procedural blocks which is always so in design as well)

To model actual behavior and represent it in a zero delay simulation, the right approach would be to model the testbench to mimic the following expected hardware behavior. In hardware:

• At the event of the clock edge, there should be no change in the input
• Data is expected to be stable much before the clock edge (setup requirement) or a while after the clock edge (hold requirement)

This can be roughly translated to:

• Assume the data that is scheduled to change right at the clock edge using verilog # delay happens only after the hold time for the previous data — We can model this by pushing this to the NonBlocking Assignment region of Verilog.
• At the same time, since we would expect the clock edge to be the first event at the current time (so that previous input state can be evaluated) — We can model this by using Blocking Assignment for Clock Generation logic in the testbench.

Now modifying the previous testbench considering the above two points:

The resulting waveform:

As we can now see, the zero delay simulation waveform represents what we would expect the behavior to be. This experiment helped me understand the essence of HDL (and why they are never to be treated like C or another programming language) both from Design as well as Testbench perspective.

The code for these examples are available here

This answer on Stack Exchange explains a similar issue in FPGA simulations.